US 12,113,531 B2
Layout structure and method for fabricating same
Yingdong Guo, Hefei (CN); Jing Xu, Hefei (CN); Wei Jiang, Hefei (CN); and Xue Shan, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 18, 2023, as Appl. No. 18/155,759.
Application 18/155,759 is a continuation of application No. PCT/CN2022/105464, filed on Jul. 13, 2022.
Claims priority of application No. 202210726154.3 (CN), filed on Jun. 24, 2022.
Prior Publication US 2023/0421157 A1, Dec. 28, 2023
Int. Cl. H03K 21/02 (2006.01); H05K 1/02 (2006.01); H04B 1/04 (2006.01)
CPC H03K 21/02 (2013.01) [H05K 1/0296 (2013.01); H04B 1/04 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A layout structure, comprising:
a frequency divider pattern layer comprising a first frequency divider region, a second frequency divider region, a third frequency divider region and a fourth frequency divider region arranged centrosymmetrically; and
a conductor pattern layer formed on the frequency divider pattern layer, the conductor pattern layer comprising a first sub-conductor pattern layer and a second sub-conductor pattern layer stacked;
wherein the first sub-conductor pattern layer is configured to communicate the first frequency divider region with the second frequency divider region, and communicate the third frequency divider region with the fourth frequency divider region; and
the second sub-conductor pattern layer is configured to communicate the first frequency divider region with the fourth frequency divider region, and communicate the second frequency divider region with the third frequency divider region;
the first frequency divider region is configured to form a first frequency divider, the second frequency divider region is configured to form a second frequency divider, the third frequency divider region is configured to form a third frequency divider, and the fourth frequency divider region is configured to form a fourth frequency divider; and
the first sub-conductor pattern layer comprises a first conductor pattern, a second conductor pattern, a third conductor pattern, and a fourth conductor pattern,
wherein the first conductor pattern communicates an output terminal of the first frequency divider with a first data input terminal of the second frequency divider;
the second conductor pattern is connected to a second data input terminal of the second frequency divider;
the third conductor pattern is connected to a second data input terminal of the fourth frequency divider; and
the fourth conductor pattern communicates an output terminal of the third frequency divider with a first data input terminal of the fourth frequency divider.