US 12,113,498 B2
Signal processing circuits and devices
Xin Zhou, Shenzhen (CN); Lei Su, Shenzhen (CN); Yuxiang Zhang, Shenzhen (CN); Meiqi Li, Shenzhen (CN); Fengyun Liao, Shenzhen (CN); and Xin Qi, Shenzhen (CN)
Assigned to SHENZHEN SHOKZ CO., LTD., Shenzhen (CN)
Filed by SHENZHEN SHOKZ CO., LTD., Guangdong (CN)
Filed on Mar. 10, 2023, as Appl. No. 18/181,575.
Application 18/181,575 is a continuation of application No. PCT/CN2021/102851, filed on Jun. 28, 2021.
Claims priority of application No. PCT/CN2020/142529 (WO), filed on Dec. 31, 2020.
Prior Publication US 2023/0216486 A1, Jul. 6, 2023
Int. Cl. A61B 5/305 (2021.01); A61B 5/00 (2006.01); H03H 11/04 (2006.01)
CPC H03H 11/04 (2013.01) [A61B 5/7225 (2013.01); A61B 5/725 (2013.01); A61B 5/305 (2021.01); H03H 2011/0488 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A signal processing circuit, comprising an analog circuit configured to process an initial signal received by the analog circuit, the initial signal comprising a target signal and a noise signal, wherein the analog circuit comprises:
a first processing circuit, configured to increase a ratio of the target signal to the noise signal and output a first processed signal; and
a second processing circuit connected to the first processing circuit, configured to amplify the first processed signal, wherein a gain multiple of the second processing circuit to the first processed signal varies with a frequency of the first processed signal, wherein:
the first processing circuit includes a common mode signal suppression circuit, a low-pass filter circuit, and a high-pass filter circuit,
the common mode signal suppression circuit is configured to suppress a common mode signal in the initial signal.