US 12,113,331 B2
System and apparatus for sequential transient liquid phase bonding
Zhizhong Tang, San Carlos, CA (US); Pradeep Srinivasan, Fremont, CA (US); Kevin Masuda, Alhambra, CA (US); and Wenjing Liang, San Jose, CA (US)
Assigned to Aeva, Inc., Mountain View, CA (US)
Filed by Aeva, Inc., Mountain View, CA (US)
Filed on Jun. 16, 2023, as Appl. No. 18/210,770.
Application 18/210,770 is a continuation of application No. 17/734,506, filed on May 2, 2022, granted, now 11,715,929.
Application 17/734,506 is a continuation of application No. 17/502,941, filed on Oct. 15, 2021, granted, now 11,362,485, issued on Jun. 14, 2022.
Prior Publication US 2023/0327395 A1, Oct. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01S 5/0237 (2021.01); B23K 1/005 (2006.01); B23K 101/40 (2006.01); H01S 5/40 (2006.01)
CPC H01S 5/0237 (2021.01) [B23K 1/0056 (2013.01); H01S 5/4025 (2013.01); B23K 2101/40 (2018.08)] 20 Claims
OG exemplary drawing
 
1. A method for performing sequential bonding, said method comprising:
receiving a substrate having a plurality of receiving pads to a stage, wherein a first and second receiving pads of said plurality of receiving pads each comprise a first metal alloy;
attaching a first semiconductor chip to said first receiving pad using a first pickup head, said first semiconductor chip comprising a first metal layer;
raising a temperature of said first semiconductor chip using a first heating unit coupled to said first pickup head according to a first temperature profile to cause intermixing of said first metal layer on said first semiconductor chip and said first metal alloy of said first receiving pad to form a second metal alloy having a higher melting point than said first metal alloy;
attaching a second semiconductor chip to said second receiving pad using a second pickup head, said second semiconductor chip comprising a second metal layer; and
raising a temperature of said second semiconductor chip by a second heating unit coupled to said second pickup head according to a second temperature profile to cause intermixing of said second metal layer on said second semiconductor chip and said first metal alloy of said second receiving pad to form a third metal alloy having a higher melting point than said first metal alloy;
wherein said first predetermined temperature profile comprises temperature set points and time durations and is substantially similar to said second predetermined temperature profile.