| CPC H01Q 5/42 (2015.01) [H01Q 5/307 (2015.01); H01Q 5/50 (2015.01); H04B 1/005 (2013.01); H04B 1/44 (2013.01)] | 20 Claims |
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1. A radio frequency integrated circuit (RFIC) comprising:
phase-locked loop (PLL) and data stream circuitry;
a plurality of tiles in communication with the PLL and data stream circuitry, wherein the plurality of tiles comprise at least one tile for each frequency band of the RFIC, wherein the plurality of tiles are configured to communicate a data stream signal through adjacent tiles of the plurality of tiles in a cascading sequence, and wherein each tile of the plurality of tiles comprises:
a plurality of up/down conversion mixers for converting the data stream signal between an intermediate frequency (IF) and a radio frequency (RF); and
a plurality of front end (FE) elements, each in communication with a corresponding antenna and an up/down conversion mixer of the plurality of up/down conversion mixers,
wherein the RFIC is a single-chip phased-array RFIC.
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