US 12,113,265 B2
Dual-stripline with crosstalk cancellation
Albert Sutono, Chandler, AZ (US); and Xiaoning Ye, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 26, 2021, as Appl. No. 17/214,111.
Prior Publication US 2022/0311114 A1, Sep. 29, 2022
Int. Cl. H01L 23/49 (2006.01); H01L 23/498 (2006.01); H01L 23/528 (2006.01); H01L 23/66 (2006.01); H01P 3/08 (2006.01); H05K 1/02 (2006.01)
CPC H01P 3/08 (2013.01) [H01L 23/49838 (2013.01); H01L 23/5283 (2013.01); H01L 23/66 (2013.01); H05K 1/0228 (2013.01); H01L 23/49822 (2013.01); H01L 2223/6627 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A printed circuit board (PCB) comprising a dual-stripline structure, the dual-stripline structure comprising:
a first region comprising a first top line vertically over a first bottom line, and a second top line vertically over a second bottom line;
a second region comprising the first top line vertically over the second bottom line, and the second top line vertically over the first bottom line; and
a transition region between the first region and the second region, wherein the first bottom line and the second bottom line cross in the transition region.