US 12,113,130 B2
Transistor and methods of forming integrated circuitry
Hung-Wei Liu, Meridian, ID (US); Sameer Chhajed, Boise, ID (US); Jeffery B. Hull, Boise, ID (US); and Anish A Khandekar, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 10, 2023, as Appl. No. 18/195,480.
Application 18/195,480 is a division of application No. 17/317,674, filed on May 11, 2021, granted, now 11,688,808.
Application 17/317,674 is a division of application No. 16/536,590, filed on Aug. 9, 2019, granted, now 11,024,736, issued on Jun. 1, 2021.
Prior Publication US 2023/0307543 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/04 (2006.01); H01L 29/66 (2006.01); H10B 12/00 (2023.01)
CPC H01L 29/7841 (2013.01) [H01L 21/02686 (2013.01); H01L 29/04 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H10B 12/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A transistor comprising:
a top source/drain region having a first conductivity-increasing dopant therein at a concentration rendering semiconductor material of the top source/drain region to be conductive;
a bottom source/drain region having a second conductivity-increasing dopant therein at a concentration rendering semiconductor material of the bottom source/drain region to be conductive;
a channel region vertically between the top and bottom source/drain regions;
a gate operatively laterally adjacent the channel region;
an upper portion of the channel region adjacent the top source/drain region having a non-conductive concentration of the first conductivity-increasing dopant therein; and
a lower portion of the channel region adjacent the bottom source/drain region having a non-conductive concentration of the second conductivity increasing dopant therein, the upper portion being vertically thicker than the lower portion.