US 12,113,129 B2
Semiconductor device, array structure of semiconductor devices, neuromorphic circuit including the semiconductor devices, and computing apparatus including the neuromorphic circuit
Jaechul Park, Yongin-si (KR); and Youngkwan Cha, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 8, 2022, as Appl. No. 17/716,460.
Claims priority of application No. 10-2021-0103477 (KR), filed on Aug. 5, 2021.
Prior Publication US 2023/0040335 A1, Feb. 9, 2023
Int. Cl. H01L 51/30 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H10B 51/30 (2023.01)
CPC H01L 29/78391 (2014.09) [H01L 29/516 (2013.01); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor layer extending in a first direction and comprising a source region and a drain region, which are apart from each other in the first direction;
an insulating layer surrounding the semiconductor layer;
a first gate electrode layer surrounding the insulating layer;
a ferroelectric layer on the first gate electrode layer; and
a second gate electrode layer on the ferroelectric layer,
wherein between the source region and the drain region, a ratio C2/C1 of a second capacitance C2 between the first gate electrode layer and the second gate electrode layer to a first capacitance C1 between the semiconductor layer and the first gate electrode layer is about 1/20 to about ⅕.