US 12,113,128 B2
DMOS transistor having thick gate oxide and STI and method of fabricating
Alexei Sadovnikov, Sunnyvale, CA (US); and Natalia Lavrovskaya, Sunnyvale, CA (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on May 25, 2021, as Appl. No. 17/330,095.
Application 17/330,095 is a division of application No. 16/179,445, filed on Nov. 2, 2018, granted, now 11,049,967.
Prior Publication US 2021/0280714 A1, Sep. 9, 2021
Int. Cl. H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7816 (2013.01) [H01L 21/28123 (2013.01); H01L 29/0653 (2013.01); H01L 29/4238 (2013.01); H01L 29/66681 (2013.01); H01L 21/28052 (2013.01); H01L 21/28211 (2013.01)] 29 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) chip having a double-diffused metal oxide silicon (DMOS) transistor, the transistor comprising:
a source region having a first dopant type;
an extended drain region coupled to a drain contact region, the extended drain region and the drain contact region having the first dopant type;
a gate region having a second dopant type that is opposite the first dopant type;
a shallow trench isolation (STI) structure overlying the extended drain region;
a gate oxide layer overlying the gate region and a portion of the extended drain region;
a gate structure on the gate oxide layer, the gate structure having a gap overlying an intersection of an edge of the STI structure with the gate oxide layer, the gap filled with a dielectric; and
a sidewall spacer on a sidewall surface of the gate structure within the gap between the dielectric and the sidewall surface.