US 12,113,119 B2
Field effect transistor, preparation method thereof and integrated circuit
Chung-Yi Chen, New Taipei (TW)
Assigned to HON HAI PRECISION INDUSTRY CO., LTD., New Taipei (TW)
Filed by HON HAI PRECISION INDUSTRY CO., LTD., New Taipei (TW)
Filed on Jan. 12, 2022, as Appl. No. 17/573,852.
Claims priority of application No. 202111020044.7 (CN), filed on Sep. 1, 2021.
Prior Publication US 2023/0069273 A1, Mar. 2, 2023
Int. Cl. H01L 29/76 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/94 (2006.01)
CPC H01L 29/66795 (2013.01) [H01L 29/0649 (2013.01); H01L 29/7848 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a field effect transistor (FET), comprising:
sequentially forming a gate electrode, a gate dielectric layer, and a channel layer on a substrate, wherein the gate electrode is closer to the substrate than the channel layer, and the channel layer is made of a two-dimensional (2D) material;
sequentially forming an insulating layer, an etching stop layer and a protective layer on the channel layer, wherein the insulating layer is in direct contact with the channel layer and is electrically insulated;
selectively etching the insulating layer, the etching stop layer, and the protective layer to form two through holes, the two through holes extending through the insulating layer, the etching stop layer, and the protective layer and exposing the channel layer;
performing a plasma treatment on the channel layer; and
forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively in a corresponding one of the two through holes and form a top contact with the channel layer.