US 12,113,117 B2
Piezo-resistive transistor based resonator with ferroelectric gate dielectric
Tanay Gosavi, Hillsboro, OR (US); Chia-ching Lin, Portland, OR (US); Raseong Kim, Portland, OR (US); Ashish Verma Penumatcha, Hillsboro, OR (US); Uygar Avci, Portland, OR (US); and Ian Young, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 3, 2023, as Appl. No. 18/130,326.
Application 18/130,326 is a division of application No. 16/238,420, filed on Jan. 2, 2019, granted, now 11,637,191.
Prior Publication US 2023/0238444 A1, Jul. 27, 2023
Int. Cl. H01L 29/51 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H03H 9/17 (2006.01)
CPC H01L 29/516 (2013.01) [H01L 27/0886 (2013.01); H01L 29/42356 (2013.01); H01L 29/78391 (2014.09); H01L 29/7851 (2013.01); H03H 9/17 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A resonator, comprising:
a plurality of gates, wherein first every other alternate gates of the plurality of gates are biased by opposite voltages, and wherein second every other alternate gates of the plurality of gates are coupled to sense circuitry, wherein the first every other alternate gates of the plurality of gates comprise a ferroelectric gate dielectric, and wherein the second every other alternate gates of the plurality of gates comprise a non-ferroelectric gate dielectric; and
a metal layer over the plurality of gates, wherein the metal layer is unbiased such that it provides a resonant cavity between the plurality of gates and the metal layer.