US 12,113,107 B2
Method for fabricating semiconductor device
Dae Won Kim, Gyeonggi-do (KR); Tae Kyun Kim, Gyeonggi-do (KR); and Dong Goo Choi, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Dec. 13, 2021, as Appl. No. 17/549,328.
Claims priority of application No. 10-2021-0055217 (KR), filed on Apr. 28, 2021.
Prior Publication US 2022/0352323 A1, Nov. 3, 2022
Int. Cl. H01L 29/40 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H10B 12/00 (2023.01)
CPC H01L 29/401 (2013.01) [H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 21/76834 (2013.01); H10B 12/09 (2023.02); H10B 12/482 (2023.02); H10B 12/485 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, the method comprising:
forming an insulating layer over a substrate, the substrate including a cell region and a peripheral region;
forming an opening by selectively etching the insulating layer over the substrate of the cell region;
forming a plug conductive layer to fill the opening and cover the insulating layer;
etching the plug conductive layer and the insulating layer over the substrate of the peripheral region by using a peri-open mask covering the cell region;
trimming the peri-open mask to expose the plug conductive layer over the substrate of a boundary region where the cell region and the peripheral region contact each other;
etching the plug conductive layer over the substrate of the boundary region by using the trimmed peri-open mask;
forming a peri-gate conductive layer over an entire surface of the substrate; and
etching the peri-gate conductive layer by using a cell open mask.