| CPC H01L 29/0696 (2013.01) [H01L 29/0843 (2013.01); H01L 24/48 (2013.01); H01L 2224/48132 (2013.01)] | 10 Claims |
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1. A semiconductor device comprising:
a gate interconnect, extending in a first direction, and configured to transmit an input signal;
a first transistor including
a plurality of gate electrodes extending in a second direction perpendicular to the first direction, and spaced apart from one another in a planar layout of the semiconductor device, and connected to the gate interconnect, and
a plurality of source regions and a plurality of drain regions which are alternately arranged along the first direction, so that each gate electrode of the plurality of gate electrodes is sandwiched between the source region and the drain region which are adjacent to each other in the planar layout of the semiconductor device;
a plurality of drain interconnects, arranged above the plurality of drain regions, and connected to the plurality of drain regions, respectively;
an output interconnect, connected to the plurality of drain interconnects, and configured to transmit an output signal output from the plurality of drain regions;
a plurality of stubs connected to the plurality of drain interconnects, respectively; and
a plurality of source interconnects arranged above the plurality of source regions, and connected to the source regions, respectively, wherein
the plurality of drain interconnects is formed by a first metal interconnect laver,
the plurality of stubs is formed by at least one of the first metal interconnect layer and a second metal interconnect layer provided above the first metal interconnect layer,
at least one stub of the plurality of stubs is connected to one drain interconnect of the plurality of drain interconnects at a first end of the one drain interconnect opposite from a second end of the one drain interconnect closer to the gate interconnect along the second direction than the first end of the one drain interconnect is to the gate interconnect in the planar layout of the semiconductor device, and
the output interconnect extends across at least one of the plurality of source interconnects and at least one of the plurality of gate electrodes of the first transistor along the first direction in the planar layout of the semiconductor device, and is connected to each of the plurality of drain interconnects.
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