US 12,113,103 B2
Charge-balance power device, and process for manufacturing the charge-balance power device
Antonello Santangelo, Belpasso (IT); Giuseppe Longo, Catania (IT); and Lucio Renna, Acireale (IT)
Assigned to STMICROELECTRONICS S.r.l., Agrate Brianza (IT)
Filed by STMICROELECTRONICS S.r.l., Agrate Brianza (IT)
Filed on Dec. 6, 2022, as Appl. No. 18/062,524.
Application 18/062,524 is a continuation of application No. 16/945,220, filed on Jul. 31, 2020, granted, now 11,538,903.
Claims priority of application No. 102019000013416 (IT), filed on Jul. 31, 2019.
Prior Publication US 2023/0107611 A1, Apr. 6, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0634 (2013.01) [H01L 21/26513 (2013.01); H01L 21/26586 (2013.01); H01L 21/266 (2013.01); H01L 29/1095 (2013.01); H01L 29/66734 (2013.01); H01L 29/7813 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A device, comprising:
a first doped layer having a first surface opposite to a second surface;
a gate region in the first doped layer, the gate region including:
a gate dielectric having a first end and a second end, the first end extending past the first surface of the first doped layer, the second end being adjacent to the second surface of the first doped layer;
a gate conductor in the gate dielectric, the gate conductor is closer to the first end than the second end, the gate conductor partially extending past the first surface of the first doped layer, and the gate conductor being completely surrounded by the gate dielectric; and
a second doped layer fully within the first doped layer, the second doped layer being on sides of the gate dielectric and being on the second end of the gate dielectric, the second doped layer terminates at ends along the sides of the gate dielectric and terminates at the ends within the first doped layer, and the ends of the second doped layer are fully covered by the first doped layer and are in direct contact with the first doped layer; and
a source region on at least one of the sides of the gate dielectric and having a third surface facing away from the first doped layer, and
wherein the gate dielectric and the gate conductor extending past the source region and extending past the third surface.