US 12,113,099 B2
Deep trench capacitor including stress-relief voids and methods of forming the same
Fu-Chiang Kuo, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jul. 26, 2023, as Appl. No. 18/359,023.
Application 18/359,023 is a division of application No. 17/458,706, filed on Aug. 27, 2021.
Prior Publication US 2023/0369388 A1, Nov. 16, 2023
Int. Cl. H01G 4/35 (2006.01); H01L 23/532 (2006.01); H01L 49/02 (2006.01); H01L 21/285 (2006.01); H01L 29/94 (2006.01)
CPC H01L 28/60 (2013.01) [H01G 4/35 (2013.01); H01L 21/2855 (2013.01); H01L 23/5329 (2013.01); H01L 28/91 (2013.01); H01L 29/945 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure, the method comprising:
forming a deep trench in a substrate;
forming a layer stack including at least three metallic electrode layers interlaced with at least two node dielectric layers over the substrate, wherein the layer stack continuously extends into the deep trench, and a cavity is present in an unfilled volume of the deep trench; and
depositing a dielectric fill material layer comprising a dielectric fill material in the cavity and over the substrate, wherein the dielectric fill material layer encapsulates a void that is free of any solid phase and is formed within a volume of the cavity such that all surfaces of the void within the dielectric fill material layer are surfaces of the dielectric fill material layer.