a package substrate including an interconnection layer;

a memory chip on the package substrate;

a molding part surrounding the memory chip;

an access terminal bonded to both the memory chip and the package substrate, the access terminal electrically connecting the memory chip to the interconnection layer of the package substrate;

an image sensor chip on the memory chip, the image sensor chip including a conductive pad and a through silicon via;

a logic chip disposed between the image sensor chip and the memory chip, the logic chip being electrically connected to the through silicon via of the image sensor chip and configured to process a pixel signal output from the image sensor chip; and

a conductive wire attached to the conductive pad of the image sensor chip, the conductive wire electrically connecting the image sensor chip to the interconnection layer of the package substrate, wherein:

the memory chip is electrically connected to the image sensor chip through the conductive wire, the memory chip being configured to store at least one of the pixel signal output from the image sensor chip and a pixel signal processed by the logic chip,

the memory chip is configured to receive the pixel signal output from the image sensor chip through the conductive wire, and

the memory chip is configured to receive the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.