US 12,113,074 B2
Semiconductor device and method for manufacturing the same
Shunpei Yamazaki, Setagaya (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Aug. 9, 2023, as Appl. No. 18/231,830.
Application 18/231,830 is a continuation of application No. 17/959,530, filed on Oct. 4, 2022, granted, now 11,749,686.
Application 17/959,530 is a continuation of application No. 17/212,083, filed on Mar. 25, 2021, granted, now 11,469,255, issued on Oct. 11, 2022.
Application 17/212,083 is a continuation of application No. 16/800,265, filed on Feb. 25, 2020, granted, now 11,101,295, issued on Aug. 24, 2021.
Application 16/800,265 is a continuation of application No. 15/925,096, filed on Mar. 19, 2018, granted, now 10,615,179, issued on Apr. 7, 2020.
Application 15/925,096 is a continuation of application No. 15/619,650, filed on Jun. 12, 2017, granted, now 9,991,288, issued on Jun. 5, 2018.
Application 15/619,650 is a continuation of application No. 14/926,722, filed on Oct. 29, 2015, granted, now 9,728,555, issued on Aug. 8, 2017.
Application 14/926,722 is a continuation of application No. 13/671,858, filed on Nov. 8, 2012, granted, now 9,202,923, issued on Dec. 1, 2015.
Application 13/671,858 is a continuation of application No. 13/613,413, filed on Sep. 13, 2012, granted, now 8,674,354, issued on Mar. 18, 2014.
Application 13/613,413 is a continuation of application No. 13/014,036, filed on Jan. 26, 2011, granted, now 8,274,079, issued on Sep. 25, 2012.
Claims priority of application No. 2010-024385 (JP), filed on Feb. 5, 2010.
Prior Publication US 2023/0387135 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 29/10 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/1225 (2013.01) [H01L 21/02554 (2013.01); H01L 21/02565 (2013.01); H01L 21/02631 (2013.01); H01L 27/1266 (2013.01); H01L 29/1033 (2013.01); H01L 29/24 (2013.01); H01L 29/66742 (2013.01); H01L 29/66969 (2013.01); H01L 29/78606 (2013.01); H01L 29/7869 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a pixel portion over the substrate; and
a driver circuit portion over the substrate,
wherein the pixel portion comprises a display element and a pixel circuit electrically connected to the display element,
wherein the driver circuit portion comprises:
a conductive layer;
a first semiconductor layer and a second semiconductor layer arranged in a first direction;
an insulating layer between the conductive layer and each of the first semiconductor layer and the second semiconductor layer;
a source electrode layer electrically connected to the first semiconductor layer and the second semiconductor layer; and
a drain electrode layer electrically connected to the first semiconductor layer and the second semiconductor layer,
wherein a part of the first semiconductor layer is included in a first transistor and a part of the second semiconductor layer is included in a second transistor,
wherein a part of the conductive layer is included in the first transistor and a part of the conductive layer is included in the second transistor,
wherein each of the first transistor and the second transistor comprises a channel formation region having a current-flow direction perpendicular to the first direction,
wherein the conductive layer extends beyond both side edges of the first semiconductor layer in the first direction,
wherein the conductive layer extends beyond both side edges of the second semiconductor layer in the first direction,
wherein the source electrode layer extends beyond the both side edges of the first semiconductor layer,
wherein the source electrode layer extends beyond the both side edges of the second semiconductor layer,
wherein the drain electrode layer extends beyond the both side edges of the first semiconductor layer,
wherein the drain electrode layer extends beyond the both side edges of the second semiconductor layer,
wherein the conductive layer includes a first region overlapping with a channel formation region of the first transistor, a second region overlapping with a channel formation region of the second transistor, and a third region not overlapping with neither the channel formation region of the first transistor nor the channel formation region of the second transistor, and
wherein, in a second direction perpendicular to the first direction, a width of the conductive layer in the third region is broader than a width of the conductive layer in the first region and a width of the conductive layer in the second region.