US 12,113,071 B2
Multi-function substrate
Eugene I-Chun Chen, Taipei (TW); Kuan-Liang Liu, Pingtung (TW); Szu-Yu Wang, Hsinchu (TW); Chia-Shiung Tsai, Hsin-Chu (TW); Ru-Liang Lee, Hsinchu (TW); Chih-Ping Chao, Hsin-Chu (TW); and Alexander Kalnitsky, San Francisco, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 21, 2022, as Appl. No. 17/869,827.
Application 17/869,827 is a division of application No. 17/189,709, filed on Mar. 2, 2021, granted, now 11,532,642.
Claims priority of provisional application 63/124,983, filed on Dec. 14, 2020.
Prior Publication US 2022/0352211 A1, Nov. 3, 2022
Int. Cl. H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01)
CPC H01L 27/1207 (2013.01) [H01L 21/76275 (2013.01); H01L 21/76283 (2013.01); H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/02658 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a polysilicon layer arranged on an upper surface of a base substrate, wherein the polysilicon layer comprises grain sizes that increase from a lower surface of the polysilicon layer to an upper surface of the polysilicon layer;
a dielectric layer arranged over the polysilicon layer;
an active semiconductor layer arranged over the dielectric layer; and
a semiconductor material arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.