CPC H01L 27/1207 (2013.01) [H01L 21/76275 (2013.01); H01L 21/76283 (2013.01); H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/02658 (2013.01)] | 20 Claims |
1. An integrated chip, comprising:
a polysilicon layer arranged on an upper surface of a base substrate, wherein the polysilicon layer comprises grain sizes that increase from a lower surface of the polysilicon layer to an upper surface of the polysilicon layer;
a dielectric layer arranged over the polysilicon layer;
an active semiconductor layer arranged over the dielectric layer; and
a semiconductor material arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.
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