US 12,113,070 B2
Transistor integration on a silicon-on-insulator substrate
Peter Baars, Dresden (DE); Viorel Ontalus, Unionville, CT (US); Ketankumar H. Tailor, Dresden (DE); Michael Zier, Dresden (DE); Crystal R. Kenney, Waterford, NY (US); and Judson Holt, Ballston Lake, NY (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Jun. 2, 2022, as Appl. No. 17/830,830.
Prior Publication US 2023/0395607 A1, Dec. 7, 2023
Int. Cl. H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01)
CPC H01L 27/1207 (2013.01) [H01L 21/84 (2013.01); H01L 29/66242 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a semiconductor substrate including a trench;
a first semiconductor layer including a portion adjacent to the trench;
a dielectric layer between the first semiconductor layer and the semiconductor substrate, the dielectric layer having an interface with the first semiconductor layer;
a second semiconductor layer in the trench, the second semiconductor layer including a first portion that is recessed relative to the interface;
a first shallow trench isolation region in the second semiconductor layer; and
a vertical heterojunction bipolar transistor including a collector in the first portion of the second semiconductor layer and a base layer, the base layer including a first portion that overlaps with the first shallow trench isolation region.