US 12,113,061 B2
Semiconductor device with linear capacitance
Tomas Palacios, Belmont, MA (US); Nadim Chowdhury, Cambridge, MA (US); and Qingyun Xie, Cambridge, MA (US)
Assigned to Massachusetts Institute of Technology, Cambridge, MA (US)
Filed by Massachusetts Institute of Technology, Cambridge, MA (US)
Filed on Apr. 8, 2021, as Appl. No. 17/225,531.
Claims priority of provisional application 63/019,588, filed on May 4, 2020.
Prior Publication US 2021/0343703 A1, Nov. 4, 2021
Int. Cl. H01L 27/06 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/778 (2006.01)
CPC H01L 27/0605 (2013.01) [H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/7786 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an active component comprising:
a first narrow-bandgap material layer; and
a first wide-bandgap material layer disposed over the first narrow-bandgap material layer and having first, second and third electrical connections with an interface between the first narrow-bandgap material layer and the first wide-bandgap material layer corresponding to a negatively charged carrier channel with a gate terminal disposed on the first wide-bandgap material layer; and
an auxiliary component comprising:
a second narrow-bandgap material layer;
a second wide-bandgap material layer disposed over the second wide-bandgap material layer with an interface between second narrow-bandgap material layer and second wide-bandgap material layer corresponding to a negatively charged carrier channel;
a third narrow-bandgap material layer disposed over the second wide-bandgap material layer with an interface between the third narrow-bandgap material layer and the second wide-bandgap material layer corresponding to a positively charged carrier channel with a gate terminal disposed on the third narrow-bandgap material layer; and
a fourth narrow-bandgap material layer disposed over the third narrow-bandgap material layer; and
a bias electrode disposed over fourth narrow-bandgap material layer; and
means for electrically connecting the gate terminal of the auxiliary component to the gate terminal of the active component.