US 12,113,056 B2
Stacked dies and methods for forming bonded structures
Cyprian Emeka Uzoh, San Jose, CA (US); Arkalgud R. Sitaram, Cupertino, CA (US); and Paul Enquist, Cary, NC (US)
Assigned to ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US)
Filed by ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US)
Filed on Dec. 22, 2022, as Appl. No. 18/145,282.
Application 18/145,282 is a continuation of application No. 17/131,329, filed on Dec. 22, 2020, granted, now 11,658,173.
Application 17/131,329 is a continuation of application No. 16/270,466, filed on Feb. 7, 2019, granted, now 10,879,226, issued on Dec. 29, 2020.
Application 16/270,466 is a continuation of application No. 15/159,649, filed on May 19, 2016, granted, now 10,204,893, issued on Feb. 12, 2019.
Prior Publication US 2023/0130580 A1, Apr. 27, 2023
Int. Cl. H01L 25/00 (2006.01); H01L 21/304 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/50 (2013.01) [H01L 21/304 (2013.01); H01L 21/306 (2013.01); H01L 21/3081 (2013.01); H01L 21/561 (2013.01); H01L 21/683 (2013.01); H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/351 (2013.01); H01L 2924/3511 (2013.01)] 53 Claims
OG exemplary drawing
 
1. A bonded structure comprising:
a carrier;
a first die layer comprising:
a first surface and a second surface opposite the first surface, the first surface directly bonded to the carrier without an intervening adhesive, the second surface comprising a first non-conductive region and a first conductive region;
a first integrated device die; and
a first protective material comprising a first layer disposed along a sidewall of the first integrated device die and a second layer on the first layer, each of the first and second layers comprising a silicon-containing inorganic dielectric material; and
a second die layer comprising:
a third surface comprising a second non-conductive region directly bonded to the first non-conductive region and a second conductive region directly bonded to the first conductive region; and
a second integrated device die.