US 12,113,052 B2
Memory devices and electronic systems
Fatma Arzum Simsek-Ege, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 20, 2023, as Appl. No. 18/491,678.
Application 18/491,678 is a continuation of application No. 17/344,519, filed on Jun. 10, 2021, granted, now 11,848,309.
Prior Publication US 2024/0047428 A1, Feb. 8, 2024
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/528 (2013.01); H01L 23/53228 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06541 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A 3D dynamic random-access memory (DRAM) device, comprising:
an array structure comprising:
a stack structure including levels of DRAM cells vertically stacked relative to one another,
the DRAM cells of each of the levels comprising:
access devices respectively comprising:
source material;
drain material;
channel material horizontally interposed between the source material and the drain material in a first direction; and
gate electrode material vertically overlying the channel material and horizontally extending in a second direction orthogonal to the first direction; and
capacitors horizontally neighboring the access devices in the first direction, the capacitors respectively vertically overlapping and coupled to the drain material of one of the access devices; and
conductive pillars vertically extending completely through the levels of DRAM cells, the conductive pillars coupled to the source material of respective ones of the access devices of the DRAM cells within the levels of DRAM cells; and
a control circuitry structure vertically overlying and directly bonded to the array structure, the control circuitry structure comprising control logic circuitry configured to effectuate control operations for the levels of DRAM cells.