CPC H01L 23/642 (2013.01) [H10B 12/30 (2023.02)] | 20 Claims |
1. A method for fabricating a semiconductor device, the method comprising:
forming a mold structure by alternately stacking mold insulating layers and semiconductor patterns in a first direction, the mold structure including a plurality of pre side extension holes defined by the semiconductor patterns and adjacent mold insulating layers, the plurality of pre side extension holes extending in a second direction perpendicular to the first direction;
forming a seed metal film along profiles of each of the pre side extension holes using a reductant having a group IVA or a group IVB element as a central atom;
forming a plurality of silicide patterns, between the mold insulating layers through a silicidation process of the seed metal film and the semiconductor patterns; and
forming a metal conductive film in a remainder of the pre side extension holes, the metal conductive film connected to the plurality of silicide patterns.
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