US 12,113,027 B2
Three-dimensional integrated circuit structures and methods of forming the same
Chung-Yu Lu, Hsinchu (TW); Ping-Kang Huang, Chiayi (TW); and Sao-Ling Chiu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 27, 2023, as Appl. No. 18/341,788.
Application 18/341,788 is a continuation of application No. 16/561,045, filed on Sep. 5, 2019, granted, now 11,728,278.
Claims priority of provisional application 62/823,005, filed on Mar. 25, 2019.
Prior Publication US 2023/0335502 A1, Oct. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/5386 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/56 (2013.01); H01L 23/49816 (2013.01); H01L 23/5385 (2013.01); H01L 25/105 (2013.01); H01L 23/5384 (2013.01); H01L 24/16 (2013.01); H01L 2224/16235 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a board substrate comprising a first group of bumps and a second group of bumps thereon:
a first semiconductor package disposed over and electrically connected to the board substrate through the first group of bumps;
a first underfill layer surrounding the first group of bumps;
a second semiconductor package disposed over and electrically connected to the board substrate through the second group of bumps;
a second underfill layer surrounding the second group of bumps; and
first and second blocking walls arranged parallel to each other, located between the first and second semiconductor packages, and in direct contact a first solder mask layer on the board substrate, wherein the first solder mask layer comprises silica, barium sulfate or epoxy resin,
wherein from a top view, a central part of a first sidewall of the first blocking wall is in direct contact with the first underfill layer while an edge part of the first sidewall of the first blocking wall is exposed from the first underfill layer, and a central part of a first sidewall of the second blocking wall is in direct contact with the second underfill layer while an edge part of the first sidewall of the second blocking wall is exposed from the second underfill layer.