US 12,113,022 B2
Semiconductor package and manufacturing method of semiconductor package
Ying-Cheng Tseng, Tainan (TW); Hao-Yi Tsai, Hsinchu (TW); Yu-Chih Huang, Hsinchu (TW); and Chia-Hung Liu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 26, 2020, as Appl. No. 16/884,035.
Prior Publication US 2021/0375765 A1, Dec. 2, 2021
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2023.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5383 (2013.01) [H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/24 (2013.01); H01L 25/167 (2013.01); H01L 23/3121 (2013.01); H01L 25/0652 (2013.01); H01L 2224/24011 (2013.01); H01L 2224/24146 (2013.01); H01L 2225/06548 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a lower encapsulated semiconductor device comprising
a first semiconductor die and a plurality of second semiconductor dies disposed around the first semiconductor die,
a carrier disposed under the first semiconductor die and
a lower encapsulating material laterally encapsulating the first semiconductor die, the plurality of second semiconductor dies, and the carrier,
wherein the first semiconductor die comprising a top surface and a bottom surface opposite to each other,
wherein each of the plurality of second semiconductor dies comprising a top surface and a bottom surface opposite to each other,
wherein the carrier comprising a top surface and a bottom surface opposite to each other,
wherein the top surface of the first semiconductor die and the top surface of each of the plurality of second semiconductor dies are coplanar,
wherein the bottom surface of the carrier and the bottom surface of each of the plurality of second semiconductor dies are coplanar,
wherein the carrier and the plurality of second semiconductor dies are arranged in a side-by-side manner, the carrier is electrically insulated from the first semiconductor die and the plurality of second semiconductor dies, and the bottom surface of the first semiconductor die is attached to the top surface of the carrier through an adhesive and in contact with the adhesive,
wherein material of the adhesive is different from material of the lower encapsulating material;
a lower redistribution structure disposed over and electrically connected to the lower encapsulated semiconductor device;
an upper encapsulated semiconductor device disposed over the lower encapsulated semiconductor device and comprising a sensor die having a pad and a sensing region, an upper encapsulating material at least laterally encapsulating the sensor die, and an upper conductive via extending through the upper encapsulating material and connected to the lower redistribution structure, wherein the sensor die completely overlaps with the first semiconductor die, and partially overlaps each of the plurality of second semiconductor dies; and
an upper redistribution structure disposed over the upper encapsulated semiconductor device, the upper redistribution structure covering the pad of the sensor die and having an opening located on the sensing region of the sensor die.