US 12,113,021 B2
Graphene-assisted low-resistance interconnect structures and methods of formation thereof
Shin-Yi Yang, New Taipei (TW); Yu-Chen Chan, Taichung (TW); Ming-Han Lee, Taipei (TW); Hai-Ching Chen, Hsinchu (TW); and Shau-Lin Shue, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 24, 2023, as Appl. No. 18/357,286.
Application 18/357,286 is a continuation of application No. 17/391,216, filed on Aug. 2, 2021, granted, now 11,710,700.
Application 17/391,216 is a continuation of application No. 16/573,817, filed on Sep. 17, 2019, granted, now 11,081,447, issued on Aug. 3, 2021.
Prior Publication US 2023/0369225 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/53276 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76805 (2013.01); H01L 21/76829 (2013.01); H01L 21/76834 (2013.01); H01L 21/76849 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first conductive feature and a second conductive feature disposed in an interlayer dielectric (ILD) layer;
a first graphene layer disposed over the first conductive feature;
a second graphene layer disposed over a portion of the second conductive feature;
an etch-stop layer (ESL) horizontally interposed between the first graphene layer and the second graphene layer, wherein a side surface of the first or the second graphene layer directly contacts a side surface of the ESL; and
a third conductive feature electrically coupled to the second conductive feature, wherein the third conductive feature is separated from the first graphene layer by a portion of the ESL, wherein the third conductive feature also directly contacts a top surface of the ESL.