US 12,113,020 B2
Formation of metal vias on metal lines
Ryan Scott Smith, Clifton Park, NY (US); Kai Wu, Palo Alto, CA (US); and Nicolas Louis Gabriel Breil, San Jose, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Feb. 24, 2021, as Appl. No. 17/184,020.
Prior Publication US 2022/0270979 A1, Aug. 25, 2022
Int. Cl. H01L 23/532 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/53266 (2013.01) [H01L 21/02183 (2013.01); H01L 21/02186 (2013.01); H01L 21/02266 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76871 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53238 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor processing method comprising:
forming a via in a semiconductor structure, wherein the via comprises a bottom surface and sidewall surfaces formed in the semiconductor structure, wherein the bottom surface exposes a copper metal line;
depositing a tantalum nitride layer on the copper metal line exposed on the bottom surface of the via, wherein the tantalum nitride layer is deposited at a temperature less than 100° C. while contacting the copper metal line;
depositing a titanium nitride layer on the tantalum nitride layer, wherein the titanium nitride layer is deposited at a temperature greater than or about 400° C. while contacting the tantalum nitride layer; and
depositing a metal on the titanium nitride layer, wherein the metal is deposited at a temperature greater than or about 300° C.