US 12,113,017 B2
Packed terminal transistors
Thomas Hua-Min Williams, Irvine, CA (US); Khaja Ahmad Shaik, Douglas (IE); Jeongah Park, San Diego, CA (US); Rinoj Thomas, Cork (IE); Harini Siddaiah, Mysore (IN); and Raj Kumar, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 17, 2022, as Appl. No. 17/651,561.
Prior Publication US 2023/0260903 A1, Aug. 17, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 29/78 (2006.01)
CPC H01L 23/528 (2013.01) [H01L 23/5226 (2013.01); H01L 29/785 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A die, comprising:
fins extending in a first direction;
a gate formed over the fins, the gate extending in a second direction that is perpendicular to the first direction;
a first source/drain contact layer formed over the fins and extending in the second direction;
a second source/drain contact layer formed over the fins and extending in the second direction, wherein the first source/drain contact layer and the second source/drain contact layer are on opposite sides of the gate;
a first source/drain metal layer electrically coupled to the first source/drain contact layer; and
a second source/drain metal layer electrically coupled to the second source/drain contact layer, wherein the first source/drain metal layer and the second source/drain metal layer do not overlap one or more of the fins.