US 12,113,015 B2
Vertical transistor fuse latches
Fatma Arzum Simsek-Ege, Boise, ID (US); and Yuan He, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 6, 2021, as Appl. No. 17/396,341.
Prior Publication US 2023/0043108 A1, Feb. 9, 2023
Int. Cl. H01L 23/525 (2006.01); G11C 29/00 (2006.01); H10B 12/00 (2023.01); G11C 11/4096 (2006.01)
CPC H01L 23/5256 (2013.01) [H10B 12/50 (2023.02); G11C 11/4096 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a substrate;
a memory array coupled with the substrate; and
a latch configured to store information from a fuse for the memory array, the latch disposed within an additional substrate above the substrate and comprising:
a plurality of p-type vertical transistors comprising a first plurality of gate terminals coupled together; and
a plurality of n-type vertical transistors comprising a second plurality of gate terminals coupled together.