US 12,112,995 B2
Low capacitance through substrate via structures
Deepak C. Pandey, Boise, ID (US); Haitao Liu, Boise, ID (US); and Chandra Mouli, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jun. 13, 2022, as Appl. No. 17/839,222.
Application 16/668,296 is a division of application No. 15/062,675, filed on Mar. 7, 2016, granted, now 10,490,483, issued on Nov. 26, 2019.
Application 17/839,222 is a continuation of application No. 16/668,296, filed on Oct. 30, 2019, granted, now 11,362,018.
Prior Publication US 2022/0310486 A1, Sep. 29, 2022
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/538 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/76898 (2013.01); H01L 23/5384 (2013.01); H01L 23/53233 (2013.01); H01L 23/53238 (2013.01); H01L 23/53252 (2013.01); H01L 23/53271 (2013.01); H01L 2223/6622 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an opening formed in a substrate, wherein the opening has at least one sidewall;
a first dielectric at least formed on the sidewall of the opening;
a first conductor at least formed on the first dielectric;
a second dielectric at least formed on the first conductor;
a second conductor at least formed on a sidewall of the second dielectric; and
a conductive coupling configured to short the first conductor to the substrate via a voltage reference node and extend across the first dielectric.