US 12,112,952 B2
Methods of forming a semiconductor device including active patterns on a bonding layer and semiconductor devices formed by the same
Sungmin Kim, Incheon (KR); and Daewon Ha, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 23, 2022, as Appl. No. 17/678,093.
Application 17/678,093 is a continuation of application No. 16/683,404, filed on Nov. 14, 2019, granted, now 11,295,958.
Claims priority of application No. 10-2019-0067894 (KR), filed on Jun. 10, 2019.
Prior Publication US 2022/0181161 A1, Jun. 9, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/306 (2006.01); H01L 21/20 (2006.01); H01L 21/3105 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01)
CPC H01L 21/30625 (2013.01) [H01L 21/2007 (2013.01); H01L 21/31051 (2013.01); H01L 21/76251 (2013.01); H01L 21/76264 (2013.01); H01L 21/845 (2013.01)] 19 Claims
OG exemplary drawing
 
19. A semiconductor device comprising:
a first bonding layer on a substrate;
a second bonding layer on the first bonding layer;
an active pattern on the second bonding layer, the active pattern having a width that decreases in a first direction toward the second bonding layer; and
a gate electrode that traverses the active pattern,
wherein an upper surface of the active pattern comprises:
converging surfaces; and
a converging edge at which the converging surfaces contact each other,
wherein the converging edge is at or adjacent to a center of the active pattern, and
the converging surfaces converge in a second direction away from the first bonding layer.