US 12,112,951 B2
Integrated dipole region for transistor
Srinivas Gandikota, Santa Clara, CA (US); Yixiong Yang, Fremont, CA (US); Steven C. H. Hung, Sunnyvale, CA (US); Tianyi Huang, Santa Clara, CA (US); and Seshadri Ganguli, Sunnyvale, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Feb. 17, 2022, as Appl. No. 17/673,905.
Prior Publication US 2023/0260791 A1, Aug. 17, 2023
Int. Cl. H01L 21/28 (2006.01); H01L 21/324 (2006.01); H01L 21/8238 (2006.01)
CPC H01L 21/28088 (2013.01) [H01L 21/28185 (2013.01); H01L 21/324 (2013.01); H01L 21/823807 (2013.01); H01L 21/823857 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method of manufacturing an electronic device, the method comprising:
depositing an interfacial layer on a top surface of a channel located between a source and a drain on a substrate;
depositing a metal film on the interfacial layer, the metal film comprising titanium aluminum (TiAl); and
depositing a high-κ dielectric layer on the metal film to form a dipole region.