US 12,112,945 B2
Semiconductor wafer, electronic device, method of performing inspection on semiconductor wafer, and method of manufacturing electronic device
Noboru Fukuhara, Ibaraki (JP); Yasuyuki Kurita, Tokyo (JP); and Takayuki Inoue, Ibaraki (JP)
Assigned to SUMITOMO CHEMICAL COMPANY, LIMITED, Tokyo (JP)
Filed by SUMITOMO CHEMICAL COMPANY, LIMITED, Tokyo (JP)
Filed on Jul. 21, 2021, as Appl. No. 17/381,992.
Application 17/381,992 is a division of application No. 16/549,906, filed on Aug. 23, 2019, granted, now 11,114,296.
Application 16/549,906 is a continuation of application No. PCT/JP2018/007058, filed on Feb. 26, 2018.
Claims priority of application No. 2017-034236 (JP), filed on Feb. 26, 2017.
Prior Publication US 2021/0358749 A1, Nov. 18, 2021
Int. Cl. H01L 21/02 (2006.01); H01L 21/66 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/423 (2006.01); H01L 29/778 (2006.01); H01L 29/78 (2006.01); G01R 31/26 (2020.01)
CPC H01L 21/02598 (2013.01) [H01L 22/34 (2013.01); H01L 29/1075 (2013.01); H01L 29/2003 (2013.01); H01L 29/42364 (2013.01); H01L 29/7786 (2013.01); G01R 31/2644 (2013.01); H01L 22/14 (2013.01); H01L 29/78 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method of performing inspection on a semiconductor wafer, the method comprising:
preparing a semiconductor wafer including a substrate, a buffer layer, a first crystalline layer, and a second layer, the substrate, the buffer layer, the first crystalline layer, and the second layer being positioned in order of the substrate, the buffer layer, the first crystalline layer and the second layer, the buffer layer and the first crystalline layer being made of a group III nitride layer, a bandgap of the first crystalline layer being smaller than a bandgap of the second layer, when the semiconductor wafer is formed as a transistor wafer, a channel of a transistor being formed at or near an interface between the first crystalline layer and the second layer;
providing a first electrode and a second electrode, electrically connected to the channel, to be closer to a front surface than the channel is and providing a third electrode, at which an electric field is applicable to a spatial region positioned between the channel and the substrate, to be closer to a back surface than the channel is;
applying negative voltage to the third electrode or applying positive voltage to the second electrode with the first electrode serving as a reference to achieve a space charge redistribution for emitting electrons and holes from a bandgap of a crystal positioned in the spatial region; and
determining that the semiconductor wafer has passed the inspection when an electron emission speed in space charge redistribution is higher than a hole emission speed, and determining that the semiconductor wafer has failed to pass the inspection when the electron emission speed in space charge redistribution is not higher than the hole emission speed.