	US 12,112,830 B2
	Methods for memory power management and memory devices and systems employing the same
Eric J. Stave, Meridian, ID (US); George E. Pax, Boise, ID (US); Yogesh Sharma, Boise, ID (US); Gregory A. King, Hastings, MN (US); Chan H. Yoo, Boise, ID (US); Randon K. Richards, Kuna, ID (US); and Timothy M. Hollis, Meridian, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Nov. 21, 2022, as Appl. No. 17/991,489.
Application 17/991,489 is a continuation of application No. 16/530,739, filed on Aug. 2, 2019, granted, now 11,508,422.
Prior Publication US 2023/0084286 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 16/10 (2006.01)

CPC G11C 7/222 (2013.01) [G11C 7/1072 (2013.01); G11C 7/1093 (2013.01); G11C 16/10 (2013.01)]

18 Claims

1. A method comprising:

receiving, from a host at a component of a memory module, an indication of a duration corresponding to enabling an input buffer of a memory device of the memory module;

reducing, in response to receiving the indication of the duration, a programmable latency of the memory device by an amount corresponding to the duration;

receiving, from the host at the component of the memory module at a first time, an enable signal for the memory device;

receiving, from the host at the component at the first time, a command/address signal for the memory device;

sending the enable signal from the component to the memory device at a second time subsequent to the first time;

enabling a disabled input buffer of the memory device in response to detecting the enable signal; and

sending the command/address signal from the component to the memory device at a third time subsequent to the second time by a delay corresponding to the duration.