US 12,112,828 B2
Modification of a command timing pattern
Carl L. Minifie, Boise, ID (US); Phong T. Nguyen, Boise, ID (US); and Alexander A. Tomaso, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 4, 2022, as Appl. No. 17/938,002.
Claims priority of provisional application 63/283,083, filed on Nov. 24, 2021.
Prior Publication US 2023/0162767 A1, May 25, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 11/4076 (2006.01)
CPC G11C 7/109 (2013.01) [G11C 7/1069 (2013.01); G11C 7/1093 (2013.01); G11C 11/4076 (2013.01)] 35 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a first activation command to activate a first set of memory cells in a first bank of a memory device;
receiving, based at least in part on the first activation command, a quantity of deselect commands, the quantity of deselect commands based at least in part on one or both of a row activation command delay or a column activation command delay, and based at least in part on one or both of a row address to column address delay or an activation command window; and
receiving, based at least in part on the deselect commands, a second activation command to activate a second set of memory cells in a second bank of the memory device.