CPC G11C 7/1039 (2013.01) [G11C 7/067 (2013.01); G11C 7/1069 (2013.01); G11C 7/12 (2013.01)] | 20 Claims |
1. A memory device comprising:
a memory group comprising a plurality of memory cells;
a control circuitry configured to read a first hard decision data entry and a first soft decision data entry together from a first memory cell among the plurality memory cells; and
a page buffer circuit coupled to the first memory cell via a bit line, the page buffer circuit comprising a plurality of data latches configured to store the first hard decision data entry and the first soft decision data entry and at least one cache latch configured to store one of the first hard decision data entry and the first soft decision data entry which are transferred from the plurality of data latches.
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