US 12,112,825 B2
Sense amplifier, memory, and control method
Hsin-Cheng Su, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/655,323
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
PCT Filed Jul. 21, 2021, PCT No. PCT/CN2021/107522
§ 371(c)(1), (2) Date Mar. 17, 2022,
PCT Pub. No. WO2022/198856, PCT Pub. Date Sep. 29, 2022.
Claims priority of application No. 202110313695.9 (CN), filed on Mar. 24, 2021.
Prior Publication US 2024/0005967 A1, Jan. 4, 2024
Int. Cl. G11C 11/4091 (2006.01); G11C 7/08 (2006.01)
CPC G11C 7/08 (2013.01) [G11C 11/4091 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A sense amplifier, comprising:
an amplification circuit, configured to amplify a voltage difference between a bit line and a reference bit line when the sense amplifier is at an amplification stage; and
a controlled power circuit, connected to the amplification circuit, and configured to determine a drive current range according to a rated compensation voltage range between the bit line and the reference bit line, and supply a drive current to the amplification circuit according to the drive current range, so as to control the amplification circuit to pull a compensation voltage between the bit line and the reference bit line to be a rated compensation voltage at an offset cancellation stage; wherein the rated compensation voltage is within the rated compensation voltage range;
wherein the controlled power circuit is configured to determine the drive current range according to the rated compensation voltage range in the following manner:
testing the sense amplifier to obtain a mapping relationship between the compensation voltage between the bit line and the reference bit line and the drive current, and
determining the drive current range according to the mapping relationship and the rated compensation voltage range.