US 12,112,823 B2
Method and system for repairing faulty cells of memory device
Helik Kanti Thacker, Bengaluru (IN); Adrita Barari, Bengaluru (IN); Ankit Gupta, Bengaluru (IN); Atishay Kumar, Bengaluru (IN); Deokgu Yoon, Suwon-si (KR); Damini, Bengaluru (IN); and Keerthi Kiran Jagannathachar, Bengaluru (IN)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 6, 2022, as Appl. No. 17/858,745.
Claims priority of application No. 202141030374 (IN), filed on Jul. 6, 2021.
Prior Publication US 2023/0019575 A1, Jan. 19, 2023
Int. Cl. G11C 29/00 (2006.01); G06N 3/063 (2023.01)
CPC G11C 29/789 (2013.01) [G06N 3/063 (2013.01); G11C 29/702 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method for repairing a memory device, comprising:
detecting one or more faulty memory cells that are faulty in a memory device and a location corresponding to each of the one or more faulty memory cells;
defining a Redundancy Analysis (RA) environment, comprising the detected location of each of the one or more faulty memory cells and a plurality of spare rows (SRs) and a plurality of spare columns (SC), for repairing the memory device;
repairing each of the one or more faulty memory cells based on an RA training process using the defined RA environment and mapping of the detected location of each of the one or more faulty memory cells with the plurality of SRs or SCs;
determining whether at least one faulty memory cell among the one or more faulty memory cells is left unrepaired after the repairing of the one or more faulty memory cells;
determining whether any SR or SC among the plurality of SRs or SCs is remaining based on the determination that the least one faulty memory cell among the one or more faulty memory cells is left unrepaired; and
training, based on the determination that indicates the at least one faulty memory cell is left unrepaired and at least one of the plurality of SRs or SCs is remaining, a first neural network (NN) such that the first NN performs an action for repairing of the one or more faulty memory cells,
wherein the action is performed such that a maximum number of faulty memory cells is reparable and a minimum number of SRs and SCs are utilized during the repairing.