US 12,112,819 B2
Apparatus for determining memory cell data states
Sheyang Ning, San Jose, CA (US); Lawrence Celso Miranda, San Jose, CA (US); Tomoko Ogura Iwasaki, San Jose, CA (US); Ting Luo, San Jose, CA (US); and Luyen Vu, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Oct. 3, 2023, as Appl. No. 18/376,198.
Application 18/376,198 is a division of application No. 17/681,976, filed on Feb. 28, 2022, granted, now 11,798,647.
Prior Publication US 2024/0029809 A1, Jan. 25, 2024
Int. Cl. G11C 29/42 (2006.01); G11C 7/10 (2006.01); G11C 29/12 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 29/12005 (2013.01); G11C 29/4401 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an array of memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to:
apply a sense voltage level to a control gate of a memory cell of the array of memory cells;
generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three;
deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell; and
deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating deactivation of the memory cell.