providing an input/output (I/O) control circuit, coupled to the flash memory controller through the specific communication interface;

providing a command register, coupled to the I/O control circuit, for buffering command information sent from the flash memory controller and transmitted through the I/O control circuit;

providing an address register, coupled to the I/O control circuit, for buffering address information sent from the flash memory controller and transmitted through the I/O control circuit;

providing a memory cell array, at least having a first plane and a second plane which is different from the first plane;

providing at least one address decoder, coupled to the memory cell array;

providing a status register, coupled to the I/O control circuit;

providing a voltage generator, coupled to the memory cell array;

using a debug circuit to generate debug information of an access operation in response to a reception of an error injection access command signal sent from the flash memory controller with controlling the voltage generator making the memory cell array generate errors; and

transmitting the generated debug information into the status register and controlling the status register transmitting the debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface;

wherein the access operation is a program operation; the debug information is associated with a true program failure, and the debug circuit controls the memory cell array generating a program failure error; the error injection access command signal sequentially comprises a specific error injection program command, address information of a specific plane, page data to be programed of the specific plane, and a change write command or a confirm command; the address information of the specific plane comprises page address, block address, die or chip address, and plane address; and, the access operation is the program operation; the debug circuit does not generate the debug information and does not control the voltage generator making the memory cell array generate errors if receiving a program command signal which sequentially comprises a program command, the address information of the specific plane, the page data to be programed of the specific plane, and the change write command or the confirm command.