	US 12,112,809 B2
	Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory
Tsung-Chieh Yang, Hsinchu (TW)
Assigned to Silicon Motion, Inc., Hsinchu County (TW)
Filed by Silicon Motion, Inc., Hsinchu County (TW)
Filed on Jul. 6, 2023, as Appl. No. 18/219,083.
Application 18/219,083 is a continuation of application No. 17/461,987, filed on Aug. 30, 2021, granted, now 11,742,030.
Application 17/461,987 is a continuation of application No. 17/024,718, filed on Sep. 18, 2020, granted, now 11,139,032, issued on Oct. 5, 2021.
Application 17/024,718 is a continuation of application No. 16/178,612, filed on Nov. 2, 2018, granted, now 10,811,104, issued on Oct. 20, 2020.
Application 16/178,612 is a continuation of application No. 15/672,318, filed on Aug. 9, 2017, granted, now 10,153,048, issued on Dec. 11, 2018.
Application 15/672,318 is a continuation of application No. 15/405,285, filed on Jan. 12, 2017, abandoned.
Application 15/405,285 is a continuation of application No. 15/170,952, filed on Jun. 2, 2016, granted, now 9,666,294, issued on May 30, 2017.
Application 15/170,952 is a continuation of application No. 14/957,563, filed on Dec. 2, 2015, granted, now 9,411,681, issued on Aug. 9, 2016.
Application 14/957,563 is a continuation of application No. 14/277,007, filed on May 13, 2014, granted, now 9,230,673, issued on Jan. 5, 2016.
Application 14/277,007 is a continuation of application No. 13/802,625, filed on Mar. 13, 2013, granted, now 8,760,929, issued on Jun. 24, 2014.
Application 13/802,625 is a continuation of application No. 13/044,548, filed on Mar. 10, 2011, granted, now 8,427,875, issued on Apr. 23, 2013.
Claims priority of provisional application 61/441,635, filed on Feb. 10, 2011.
Claims priority of provisional application 61/420,336, filed on Dec. 7, 2010.
Prior Publication US 2023/0352101 A1, Nov. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 3/06 (2006.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 29/52 (2006.01); H03M 13/15 (2006.01)

CPC G11C 16/26 (2013.01) [G06F 3/0619 (2013.01); G06F 3/064 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G06F 11/1072 (2013.01); G11C 11/5642 (2013.01); G11C 16/0483 (2013.01); G11C 16/3427 (2013.01); G11C 29/52 (2013.01); H03M 13/152 (2013.01); G11C 16/0475 (2013.01); G11C 2211/5644 (2013.01); G11C 2211/5648 (2013.01)]

9 Claims

1. A memory controller for reading data stored in a flash memory,

wherein the memory controller is configured to perform the steps of:

reading a plurality of memory cells of the flash memory by using a plurality of control gate voltages to obtain a plurality of bit sequences from the flash memory;

referring to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a first control gate voltage and a second control gate voltage of the plurality of control gate voltages, to generate a first value;

referring to the plurality of bit sequences to determine numbers of memory cells whose threshold voltages are located between a third control gate voltage and a fourth control gate voltage of the plurality of control gate voltages, to generate a second value; and

updating at least one of the plurality of control gate voltages according to the first value and the second value.