US 12,112,806 B2
Nonvolatile memory device and method of programming in the same
Yo-Han Lee, Incheon (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 2, 2023, as Appl. No. 18/205,149.
Application 18/205,149 is a continuation of application No. 17/672,122, filed on Feb. 15, 2022, granted, now 11,699,489.
Application 17/672,122 is a continuation of application No. 17/007,767, filed on Aug. 31, 2020, granted, now 11,282,575, issued on Mar. 22, 2022.
Application 17/007,767 is a continuation in part of application No. 16/393,377, filed on Apr. 24, 2019, granted, now 10,847,228, issued on Nov. 24, 2020.
Claims priority of application No. 10-2018-0135905 (KR), filed on Nov. 7, 2018.
Prior Publication US 2023/0307057 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/20 (2006.01); G11C 16/24 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/20 (2013.01); G11C 16/24 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of programming a memory block comprising a plurality of stacks connected in series in a vertical direction by forming a plurality of cell strings between a plurality of bitlines and a source line, the method comprising:
determining, from among the plurality of stacks, a first stack comprising memory cells to be programmed, the first stack being separated from a second stack by a boundary portion comprising a plurality of intermediate switching transistors;
during a first period, applying a turn-on voltage to gate electrodes of the plurality of intermediate switching transistors;
during the first period, applying a first pass voltage to wordlines of the second stack;
during a second period after the first period, applying a turn-off voltage to the gate electrodes of the plurality of intermediate switching transistors while maintaining the first pass voltage applied to the wordlines of the second stack;
during the second period, applying a second pass voltage to wordlines of the first stack; and
during a program execution period after the second period, applying a program voltage to a selected wordline of the first stack.