US 12,112,802 B2
Memory device, the operation method thereof and memory system
Zhihong Li, Wuhan (CN); Jing Wei, Wuhan (CN); and Masao Kuriyama, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Oct. 26, 2022, as Appl. No. 17/974,271.
Claims priority of application No. 202210864398.8 (CN), filed on Jul. 21, 2022.
Prior Publication US 2024/0029793 A1, Jan. 25, 2024
Int. Cl. G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/0433 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising a memory cell array and a peripheral circuit coupled to the memory cell array;
the memory cell array comprises a plurality of memory planes;
the peripheral circuit comprises a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane;
the plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits;
during a program operation, the plurality of memory planes share the plurality of selected voltage selection circuits; and
during a read operation, each memory plane uses a part of the plurality of selected voltage selection circuits respectively to perform voltage selection.