US 12,112,801 B2
Forward looking algorithm for vertical integrated cross-point array memory
Ferdinando Bedeschi, Biassono (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 26, 2022, as Appl. No. 17/897,021.
Prior Publication US 2024/0071488 A1, Feb. 29, 2024
Int. Cl. G11C 7/14 (2006.01); G11C 13/00 (2006.01); G11C 16/28 (2006.01)
CPC G11C 13/0035 (2013.01) [G11C 13/0004 (2013.01); G11C 13/004 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for reading a memory array having a first and second plurality of cells, the method comprising:
applying a first ramping voltage with a first predetermined increment for each of a plurality of ramping steps of the first ramping voltage to read the first plurality of cells;
counting, among the first plurality of cells at each ramping step of the first ramping voltage, a first number of cells at a logic 1 state;
comparing the first number with a first predetermined threshold at each ramping step of the first ramping voltage;
determining a first voltage reached by the first ramping voltage, at the first voltage the first number becoming equal to or higher than the first predetermined threshold;
applying a second voltage to read the second plurality of cells, the second voltage being lower than the first voltage by a first predetermined amount; and
applying a second ramping voltage ramping up from the second voltage with a second predetermined increment for each ramping step to read the second plurality of cells, the second predetermined increment being lower than the first predetermined increment by a second predetermined amount.