US 12,112,800 B2
High speed multi-level cell (MLC) programming in non-volatile memory structures
Xiang Yang, Santa Clara, CA (US); Deepanshu Dutta, Fremont, CA (US); Muhammad Masuduzzaman, Chandler, AZ (US); and Jiacen Guo, Cupertino, CA (US)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on May 26, 2022, as Appl. No. 17/825,048.
Prior Publication US 2023/0386568 A1, Nov. 30, 2023
Int. Cl. G11C 11/04 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01)
CPC G11C 11/5628 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for programming a memory array of a non-volatile memory structure, comprising:
initiating a programming operation with respect to a population of MLC type memory cells, wherein the programming operation comprises programming:
a first programmable state according to a first programming voltage;
a second programmable state according to a second programming voltage; and
a third programmable state according to a third programming voltage, wherein (i) a magnitude of the second programming voltage is greater than a magnitude of the first programming voltage, and (ii) a magnitude of the third programming voltage is greater than the magnitude of the second programming voltage;
in a first program pulse, programming one or more selected memory cells from an erased data state to the first programmable state and programming one or more selected memory cells to the second programmable state; and
in a second program pulse, programming one or more selected memory cells according to the third programmable state.