US 12,112,798 B2
Output circuitry for non-volatile memory array in neural network
Farnood Merrikh Bayat, Goleta, CA (US); Xinjie Guo, Goleta, CA (US); Dmitri Strukov, Goleta, CA (US); Nhan Do, Saratoga, CA (US); Hieu Van Tran, San Jose, CA (US); Vipin Tiwari, Dublin, CA (US); and Mark Reiten, Alamo, CA (US)
Assigned to SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US); and The Regents of the University of California, Oakland, CA (US)
Filed on Mar. 20, 2023, as Appl. No. 18/123,918.
Application 18/123,918 is a division of application No. 17/238,077, filed on Apr. 22, 2021, granted, now 11,790,208.
Application 17/238,077 is a continuation of application No. 15/594,439, filed on May 12, 2017, granted, now 11,308,383, issued on Apr. 19, 2022.
Claims priority of provisional application 62/337,760, filed on May 17, 2016.
Prior Publication US 2023/0229887 A1, Jul. 20, 2023
Int. Cl. G11C 11/54 (2006.01); G06F 3/06 (2006.01); G06N 3/04 (2023.01); G06N 3/045 (2023.01); G06N 3/063 (2023.01); G11C 16/08 (2006.01); G11C 16/12 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01); G11C 29/38 (2006.01)
CPC G11C 11/54 (2013.01) [G06F 3/061 (2013.01); G06F 3/0655 (2013.01); G06F 3/0688 (2013.01); G06N 3/04 (2013.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G11C 16/08 (2013.01); G11C 16/12 (2013.01); G11C 16/16 (2013.01); G11C 16/3436 (2013.01); G11C 29/38 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A circuit for converting a current in a neural network into an output voltage, comprising:
a non-volatile memory cell comprises a word line terminal, a bit line terminal, and a source line terminal, wherein the bit line terminal receives the current; and
a switch for selectively coupling the word line terminal to the bit line terminal;
wherein when the switch is closed, the current flows into the non-volatile memory cell and the output voltage is provided on the bit line terminal.