US 12,112,793 B2
Signal routing between memory die and logic die for mode based operations
Aliasger T. Zaidy, Seattle, WA (US); Glen E. Hush, Boise, ID (US); Sean S. Eilert, Penryn, CA (US); and Kunal R. Parekh, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 10, 2022, as Appl. No. 17/885,374.
Claims priority of provisional application 63/231,660, filed on Aug. 10, 2021.
Prior Publication US 2023/0051480 A1, Feb. 16, 2023
Int. Cl. G11C 11/4093 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01); G16B 30/00 (2019.01); G16B 50/10 (2019.01); H01L 21/66 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC G11C 11/4093 (2013.01) [G06F 3/0656 (2013.01); G06F 13/1673 (2013.01); G06F 13/28 (2013.01); G11C 7/08 (2013.01); G11C 7/1039 (2013.01); G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); G16B 30/00 (2019.02); G16B 50/10 (2019.02); H01L 21/78 (2013.01); H01L 22/12 (2013.01); H01L 24/08 (2013.01); H01L 24/48 (2013.01); H01L 24/80 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); G06F 2213/28 (2013.01); H01L 24/16 (2013.01); H01L 2224/0801 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/1601 (2013.01); H01L 2224/16221 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48221 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14335 (2013.01); H01L 2924/1436 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A method comprising:
storing, at a buffer of a logic die that is bonded to a memory die via a wafer-on-wafer bonding process, signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and the memory die;
receiving, at the logic die, signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond;
performing, at the logic die, a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data; and
providing results of the plurality of operations to the buffer based on a mode of the logic die and a type of the plurality of operations, wherein the mode of the logic die is used to identify the type of the plurality of operations.