US 12,112,792 B2
Memory device for wafer-on-wafer formed memory and logic
Glen E. Hush, Boise, ID (US); Sean S. Eilert, Penryn, CA (US); Aliasger T. Zaidy, Seattle, WA (US); and Kunal R. Parekh, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 4, 2022, as Appl. No. 17/712,935.
Claims priority of provisional application 63/231,660, filed on Aug. 10, 2021.
Prior Publication US 2023/0051863 A1, Feb. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); G16B 30/00 (2019.01); G16B 50/10 (2019.01); H01L 21/66 (2006.01); H01L 21/78 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC G11C 11/4093 (2013.01) [G06F 3/0656 (2013.01); G06F 13/1673 (2013.01); G06F 13/28 (2013.01); G11C 7/08 (2013.01); G11C 7/1039 (2013.01); G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); G16B 30/00 (2019.02); G16B 50/10 (2019.02); H01L 21/78 (2013.01); H01L 22/12 (2013.01); H01L 24/08 (2013.01); H01L 24/48 (2013.01); H01L 24/80 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); G06F 2213/28 (2013.01); H01L 24/16 (2013.01); H01L 2224/0801 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/1601 (2013.01); H01L 2224/16221 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48221 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14335 (2013.01); H01L 2924/1436 (2013.01)] 28 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an array of memory cells configured on a memory die and coupled to sense lines and access lines of the memory die;
a respective sense amplifier configured on the memory die and coupled to each of the sense lines;
a respective local input/output (I/O) line on the memory die and coupled to each of a plurality of subsets of the sense lines for communication of data on the memory die; and
a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more devices off the memory die, wherein:
the respective transceiver is configured to route the data to the one or more devices off the memory die through the respective local I/O line in response to receipt of a first signal from a controller; and
the respective transceiver is configured to route the data to one or more devices off the memory die through a wafer-on-wafer bond in response to the respective transceiver receiving a second signal from the controller.