US 12,112,715 B2
Reflective display mirror hinge memory reduction systems and methods
Denis M Darmon, Boulder, CO (US); Kanghoon Jeon, San Jose, CA (US); Jose A Dominguez-Caballero, San Jose, CA (US); and Bilin Wang, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jul. 17, 2023, as Appl. No. 18/353,622.
Claims priority of provisional application 63/376,548, filed on Sep. 21, 2022.
Prior Publication US 2024/0096294 A1, Mar. 21, 2024
Int. Cl. G02B 26/08 (2006.01); G09G 3/34 (2006.01); H04N 11/20 (2006.01)
CPC G09G 3/346 (2013.01) [G02B 26/0833 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0626 (2013.01); G09G 2330/021 (2013.01); G09G 2370/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device comprising:
an electronic display configured to display a plurality of image frames, wherein the electronic display comprises:
one or more illuminators configured to generate light during emission periods of the plurality of image frames; and
a plurality of mirrors configured to selectively direct the light to a plurality of pixel locations of the electronic display based on a plurality of bitplanes, wherein each bitplane of the plurality of bitplanes sets an arrangement of the plurality of mirrors; and
duty cycle balancing circuitry configured to generate and provide duty cycle balancing signals to the electronic display, wherein, in response to the duty cycle balancing signals, the electronic display is configured to implement balancing on bitplanes during at least a first portion of off periods of the plurality of image frames and balancing off bitplanes during at least a second portion of the off periods of the plurality of image frames such that, in an aggregate, a ratio of respective on times of the plurality of mirrors to respective off times of the plurality of mirrors is balanced across the plurality of image frames during the off periods.