US 12,112,706 B2
Pixel circuit configured to control light-emitting element
Jiro Yanase, Kanagawa (JP); and Yojiro Matsueda, Kanagawa (JP)
Assigned to WUHAN TIANMA MICRO-ELECTRONICS CO., LTD., Wuhan (CN)
Filed by WUHAN TIANMA MICRO-ELECTRONICS CO., LTD., Wuhan (CN)
Filed on Apr. 28, 2023, as Appl. No. 18/308,829.
Application 18/308,829 is a division of application No. 17/867,254, filed on Jul. 18, 2022, granted, now 11,676,539.
Claims priority of application No. 2021-120819 (JP), filed on Jul. 21, 2021; and application No. 2022-066566 (JP), filed on Apr. 13, 2022.
Prior Publication US 2023/0267889 A1, Aug. 24, 2023
Int. Cl. G09G 3/325 (2016.01)
CPC G09G 3/325 (2013.01) [G09G 2320/046 (2013.01); G09G 2330/021 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A pixel circuit configured to control light emission of a light-emitting element, the pixel circuit comprising:
a light-emitting element;
a driving transistor configured to control driving current for the light-emitting element;
a first capacitive element and a second capacitive element connected in series between a gate of the driving transistor and a positive power line;
a first switching transistor configured to switch connection/disconnection between the gate of the driving transistor and a data line;
a second switching transistor configured to switch supply/non-supply of electric current from the positive power line to the driving transistor;
a connection line connecting an intermediate node located between the driving transistor and the second switching transistor and an intermediate node located between the first capacitive element and the second capacitive element;
a third switching transistor configured to switch connection/disconnection between the gate of the driving transistor and a reference power line;
a fourth switching transistor configured to switch supply/non-supply of electric current from the driving transistor to the light-emitting element; and
a fifth switching transistor configured to switch connection/disconnection between a reset power line and an intermediate node located between the driving transistor and the fourth switching transistor,
wherein, during an initialization period, the first switching transistor is OFF and the second switching transistor, the third switching transistor, the fourth switching transistor, and the fifth switching transistor are ON,
wherein, during a threshold compensation period following the initialization period, the third switching transistor and the fifth switching transistor are ON and the first switching transistor, the second switching transistor, and the fourth switching transistor are OFF,
wherein, during a data write period following the threshold compensation period, the first switching transistor is ON and the second switching transistor, the third switching transistor, the fourth switching transistor, and the fifth switching transistor are OFF, and
wherein, during an emission period following the data write period, the second switching transistor and the fourth switching transistor are ON and the first switching transistor, the third switching transistor, and the fifth switching transistor are OFF.