US 12,112,705 B2
Pixel, display device, and method of driving display device
Hanbit Kim, Seoul (KR); Taewook Kang, Seongnam-si (KR); Doo-Na Kim, Seongnam-si (KR); Sangsub Kim, Suwon-si (KR); Yunjung Oh, Anyang-si (KR); Dokyeong Lee, Yongin-si (KR); and Jaehwan Chu, Hwaseong-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do (KR)
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
Filed on Oct. 3, 2023, as Appl. No. 18/376,160.
Application 18/376,160 is a continuation of application No. 17/741,833, filed on May 11, 2022, granted, now 11,810,511.
Claims priority of application No. 10-2021-0111960 (KR), filed on Aug. 24, 2021.
Prior Publication US 2024/0029655 A1, Jan. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/32 (2016.01); G09G 3/3241 (2016.01); G09G 3/3291 (2016.01)
CPC G09G 3/3241 (2013.01) [G09G 3/3291 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/027 (2013.01); G09G 2330/021 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A pixel comprising:
an organic light-emitting diode including a first terminal electrically connected to an output node and a second terminal electrically connected to a second power supply voltage line;
a driving transistor including a first terminal electrically connected to an input node, a second terminal electrically connected to the output node, and a gate terminal electrically connected to a control node;
a first dual gate transistor electrically connected between the control node and the second terminal of the driving transistor, the first dual gate transistor including a first sub-transistor and a second sub-transistor which are connected in series;
a first capacitor including a first electrode electrically connected to a first power supply voltage line and a second electrode electrically connected to a first node which connects the first and second sub-transistors to each other; and
a compensation transistor including a first terminal to which a compensation voltage is applied, a second terminal electrically connected to the first node, and a gate terminal to which a compensation gate signal is applied.